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What is High-Bandwidth Memory (HBM)?

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Engineering Notes · AI Systems

The spec sheet led with the accelerator's high-bandwidth memory, and only then mentioned its processing speed.

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Overview

High-bandwidth memory, or HBM, is computer memory built as a stack of chips placed on the same slab as the processor, joined to it by more than a thousand wires that all carry data at once. For comparison, an ordinary memory channel runs on 64 wires. The width exists because a modern processor can finish its arithmetic before a narrow connection delivers the next batch of numbers, so delivery, not arithmetic, often sets the pace. HBM widens that delivery, and being built onto the same slab keeps every trip short too. It changes how quickly numbers reach the chip, not what the chip can do with them.
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Overview

High-bandwidth memory, HBM, is why an AI chip's spec sheet brags about its memory before its math. The multiplying part has been absurdly quick for years; the contest now is the supply of numbers. So the memory got piled into towers, glued right onto the same package, and wired ridiculously wide. And capacity is blunt: a model that needs 80 gigabytes either fits inside the tower or that chip is out of the running. Smarter silicon? No. Memory wide enough, and close enough, to keep up? Entirely. 😎

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Detail

High-bandwidth memory is memory redesigned around one problem: processors got faster at arithmetic than ordinary memory got at supplying the numbers they work on. That gap has a name: the memory wall, and for much of the work an AI chip does, the wall, not arithmetic speed, is the limit. HBM answers the wall in two ways. First, width. Pushing a narrow connection to run ever faster costs power and gets harder with each step, so HBM runs more than a thousand wires side by side instead. The gain comes from the count of wires, not the pace of any one. Second, nearness. The memory chips are stacked into a tower and placed on the same slab of silicon as the processor, so every trip the data makes is short and cheap. Here is what that combination gets you. In the simplest case, a model whose numbers fill 100 gigabytes is read in full for every word it writes. Memory that moves 2 terabytes each second is moving 2,000 gigabytes, so it completes that 100-gigabyte read 20 times a second. That is the ceiling: 20 words a second, and faster arithmetic cannot raise it. Only wider, closer memory can. That is why an AI chip's memory figures sit beside its speed figures on every specification, and why this memory cannot be added later: it is built into the processor's package, not plugged into a slot.
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Detail

High-bandwidth memory is a tower of memory glued millimetres from an AI chip, and it exists because the slow part of computing moved. Chips became so quick at multiplication that the real question turned into how fast you can shovel material in. So picture two accelerators with identical math engines, where A's memory shifts data twice as quickly as B's. A language model of the common kind has to read all of itself for each word of the answer, so on the same model, A talks at 30 words a second and B at 15. Half the delivery, half the conversation, all of the difference. The math never differed. The delivery did, and the delivery won. So buying double the compute on yesterday's memory buys you exactly nothing. That is also why the memory, not the logic, became the scarce and fought-over part of the AI hardware business. The first question asked of any new accelerator is not how clever it is. It is how much the thing can hold and how quickly it can pour what it holds. 😎

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Analogy

High-bandwidth memory is a wider packing bench, set right beside the shelves. Two warehouse workers pack orders with the same quick hands. One has a narrow bench that holds a handful of items, a storeroom down the corridor, and a shift that is mostly walking: pack a little, walk, restock, walk back. The other has a bench three times as wide, stacked with everything her next orders need, an arm's reach from the racks. She ships far more parcels per hour without packing any faster, because packing was never the slow part. Fetching was. That is HBM: the same worker, a wider surface, a shorter walk.
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Analogy

High-bandwidth memory is the lesson of the fancy new drive on the old cable. The drive is rated blazing fast, and the progress bar still says 40 minutes, because every byte squeezes through one skinny connection and the connection sets the pace. Nothing is broken. Both ends are quick; the path between them is not. Swap in a proper cable and the same copy takes 4 minutes. HBM is that swap performed on a processor's memory, times a thousand: a wider, shorter path, and suddenly the fast parts are allowed to be fast. 😎

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Formal definition — The same term, explained the usual way

High-bandwidth memory (HBM) is a form of DRAM in which memory chips are stacked vertically and interconnected by through-silicon vias, fine conductors running through the chips themselves. The stack is mounted alongside the processor within a shared package and communicates over an exceptionally wide interface: 1,024 bits under the original JEDEC standard of 2013, against 64 bits for a standard DDR channel, with later generations wider still. The arrangement yields very high aggregate bandwidth at low energy per bit transferred, and it has become the standard memory in AI accelerators, and in the smaller set of other high-performance processors that can justify its cost.

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